1. Field of the Invention
The present invention generally relates to current controlled devices and more particularly to current controlled Silicon on Insulator (SOI) devices that may be suitable for use as Electrostatic discharge (ESD) protect devices for CMOS Integrated Circuits (ICs).
2. Background Description
Integrated Circuit (IC) chips made in the complementary insulated gate Field Effect Transistor (FET) technology, commonly referred to as CMOS, are very sensitive to ElectroStatic Discharge (ESD). A single ESD event can destroy circuit FETs, thereby rendering a typical CMOS IC useless. An electrical charge can accumulate on the surface of gate conductors, for example, to create a breakdown oxide electric field where large currents experienced in an ESD event damage the respective device. Consequently, ESD is a significant reliability concern in the processing and handling these delicate semiconductor devices, and especially for state of the art ultra-thin thin oxide CMOS technologies.
Normally, after manufacture is completed, IC chips are packaged inside a ceramic or plastic package that has wiring leads connecting package pins and chip Input/Output (I/O) pads. Consequently, floating gates connected to I/O pads remain particularly vulnerable to ESD. To mitigate this ESD problem, IC chips normally have ESD protection devices at chip pads. The ESD protect devices shunt destructive high current away from connected devices.
Historically, older bulk FET chips relied upon Silicon Controlled Rectifiers (SCRs) for adequate ESD protection. A typical SCR protect device acts as a high-performance, high-current clamp that can redirect ESD currents away from vulnerable devices at low turn-on or clamping voltages and under short response times. Unfortunately, a phenomenon known as latch-up is a common design problem in legacy bulk CMOS technologies. Latch-up occurs when PFETs and NFETs are placed too close together on a bulk substrate, such that a parasitic horizontal SCR forms by the placement. Noise can turn on the horizontal SCR, which clamps the FET back bias voltages together and typically destroys the chip. Eliminating latch-up (and reducing device capacitances for better performance) was one of the primary motivations for migrating CMOS to Silicon Insulator (SOI).
Substantially eliminating intrinsic SCRs by migrating to SOI has made providing suitable ESD protect devices much more difficult. Bulk CMOS SCR designs do not work well in SOI because, by the very nature of the technology, device N and P features on the SOI surface layer are fully isolated from each other. Consequently, designing a conventional SCR structure in SOI requires large tracts of valuable chip active area.
Thus, there is a need for a relatively small ESD protection device for ultra-thin oxide technologies such as for SOI CMOS chips, and in particular for such an SCR that occupies very little chip active area.